A typical phase-locked loop includes a voltage-controlled oscillator which produces a clock output as well as an output signal which is fed to a phase detector for comparison with an input signal. The output of the phase detector is then filtered and fed back as an error signal to control the voltage-controlled oscillator.
In prior art phase locked loops, the threshold of the amplifier has been designed so as to amplify the average varying DC voltage component of the output of the phase detector and thereby produce a beat frequency signal when the loop is operating in an out-of-lock condition. Typical of these designs is the requirement to adjust the threshold of the amplifier so as not to amplify the undesired DC components which may be caused by circuit imbalances. These imbalances are produced by variations in temperature, supply voltage drift or aging of the circuit components.
Other prior art phase-locked loops feature a non-harmonic phase detector for signal acquisition and a harmonic type phase detector which is switched in to maintain lock during processing of complex data patterns. This dual phase detector scheme is partially required by the above-described circuit imbalances.
Still other conventional phase-locked loops are characterized by the production of a low-amplitude beat frequency signal at the output of the phase detector which, due to these circuit imbalances, makes signal acquisition in the loop a precarious procedure.